Debug FPGA projects using machine learning

Black-Box verification is most valuable verification technique, but the hardest one. However, in simulation, as opposite to FPGA devices, there is possibility to have access at all input and output signals of verified module. Due to limited number of input/output ports, FPGA device does not offer this advantage; it allows only a small amount of connections between its ports and external data collector to be established. In this paper we propose a different way of debugging an FPGA device which consists in collection of data from FPGA ports through an UART connection, processing of data in order to make it readable and affordable for analysis and usage of obtained information for training machine learning models in order to check hardware functionality.