A Seamless, Reconfigurable, and Highly Parallel In-Memory Stochastic Computing Approach With Resistive Random Access Memory Array

A seamless, reconfigurable, and highly parallel in-memory stochastic computing (SC) approach is proposed and experimentally demonstrated in resistive random access memory (RRAM) array. By utilizing the probabilistic switching behavior of RRAM and parallel writing, stochastic bit streams (SBS) are generated in parallel. By employing in-memory stateful logic, parallel stochastic logic is directly performed within the same memory array. This in-memory SC approach has three merits: 1) true stochastic number generator (SNG) can be obtained with low cost, 2) the signal conversion overhead between SNG and stochastic logic is eliminated, 3) it is highly parallel and the stochastic logic is reconfigurable. This work provides an efficient and low-cost alternative approach to achieve SC.