Machine Instruction Analysis for DCT Algorithm using DLX Architecture

One of the methods to reduce the size of images is by compressing the images. This research tried to find out the machine instruction set of DLX microprocessor to do image compression, in which the result will be used to design an ASIP microprocessor that has less power consumption compared to a general-purpose microprocessor with dozens of machine instruction. This ASIP microprocessor will become the heart of our next project, which is the autonomous seabed robot scanner that will be installed under the sea which relying on a rechargeable battery to supply the power. That is why this research is very crucial to reduce the power consumption of the microprocessor to save more energy for long term use. This research uses a simulation tool for DLX microprocessor, namely the WinDLX, to implement the algorithm of Discrete Cosine Transform (DCT) for image compression process. The result shows that the program requires a total of 14763 cycles executed with a total of 5920 instructions. The instructions which are often used in this experiment are LF (Load Float) which is used to load the value of matrices before being stored in the memory and multiplied to other matrices.