Design of a low power, high speed self calibrated dynamic latched comparator

A Dynamic Comparator is an important part of the analog-to-digital converter (ADC). The performance and accuracy of ADC depends on the design of comparator. Moreover, comparator is the most power-hungry among all other parts of ADC. To satisfy speed and accuracy within a low power budget requirements, a PMOS based Double tail latch type Comparator circuit has been presented in this work. Detail analysis of offset voltage of the dynamic latched comparator has been carried out in this work. A Foreground calibration technique is used in this work to minimize the offset. The entire architecture is designed and simulated in CADENCE Virtuoso using UMC 180 nm PDK with 1.8 V power supply. Transient and statistical measurements have been carried out to test the performance of the circuit under the impact of process variations, temperature and mismatches. Post-layout simulation shows that the comparator achieves 200 μV resolution with 13 bit precision at a frequency of 50 MHz while dissipating 6.68 μW from 1.8 V supply with 0.074 mm² area consumption.