Power Plane Defect Findings in Silicon with Lock- In Thermography & OBIRCH/TIVA Techniques

In this work, we present a study on power plane defect findings using both lock-in thermography & OBIRCH / TIVA techniques on Intel 14 nm & Intel 10 nm products. By using lock-in thermography, defect localization of a short defect in the silicon can be achieved quickly in macroscopic view. The use of OBIRCH / TIVA technique allows the defect to be localized down to sub-micron region with a solid-immersion lens. Combining both techniques generate significant time saving in the fault isolation process, especially on multi-chip packaging with 2 or more silicon. 3 different defect modes are being discussed, including (1) silicon damage at diffusion, and (2) metal-insulator-metal damage, and (3) metal stacked damage without diffusion damage. Additional discussion and benefits of using both backside & frontside lock-in thermography fault isolation techniques are also being presented.