A Double Balanced Mixer with Folded Structure and Variable-Conversion gain in 65nm CMOS

In this paper, a mixer with radio frequency (RF) input signal in the range of 9.5GHz to 10.5GHz and intermediate frequency (IF) in the range of 0.5GHz to 1.5GHz is designed. The proposed mixer has the variable conversion gain that not only ensures the appropriate performance of the system in face with large signals, but also increases the dynamic range of the receiver. With novel structure, the gain variation of sub-blocks does not destroy the other system parameters. In the proposed circuit, the PMOS switches are selected in order to improve the design of variable conversion gain and decrease its flicker noise. By DC coupling, the first stage, in which convert the RF voltage into current, is separated from the switching stage that cause the separation of biasing current of these two stages. Therefore, for the aim of reaching high conversion gain, the current of first stage is selected large as much as possible. In addition, the low noise amplifier with the suitable transconductance is used in this stage. With the help of two inductors, the effect of parasitic capacitors that bypass the signals is eliminated. In the proposed circuit, the conversion gain with the variation of the controlled voltage is changed between 2.94dB to 17dB. Its noise figure is less than 11dB, while its IIP3 is -0.6dBm and its power dissipation is 7.8mW. These results are achieved while this circuit is only occupied 0.1mm
₂
chip areas. The post layout simulation of the proposed structure is done in TSMC 65nm CMOS technology.