A Resource-Efficient Parallel Connected Component Labeling Algorithm and Its Hardware Implementation

Connected Component labeling (CCL) is usually time-consuming, so a dedicated hardware accelerator of CCL is essential in the embedded vision and multimedia system. In this paper, we propose a single-scan resource-efficient parallel CCL algorithm. Our CCL method scans two adjacent rows simultaneously to extract runs and detect equivalent runs; an equivalent label set is used to resolve equivalences. After each row scan, the finished objects are output in time, and the freed memory resources are reused to reduce memory requirements. Both pixel-based labeled image (PLI) and run-based labeled image (RLI) can be generated by our CCL method. In addition, the steps of our CCL method are executed concurrently to improve labeling performance. The hardware architecture based on our CCL method is implemented with Verilog. The evaluation results illustrate that our CCL architecture can label more than 40 2048 × 1536 benchmark images per second on average, and outperforms previous CCL architectures in terms of labeling performance or memory resource consumption.