Design and Implementation of a 32-bit ISA RISC-V Processor Core using Virtex-7 and Virtex- UltraScale

In this paper, a 32-bit Datapath with RISC-V instruction set architecture based on RV32I CPU instruction set has been designed. Furthermore, through analysis of function and theory of RISC-V CPU instruction set, the processor has been optimized by designing a six staged folded pipeline core. Finally, the design has been examined on the current industrial standards FPGA boards. Synthesis and implementation on two Boards of Virtex family has been compared on the basis of Utilization reports and Power Reports. The comparison shows the more heavily configurable board i.e. the Virtex Ultrascale delivers better power - performance tradeoff at higher costs.