The FPGA Implementation of Neural Network-Based Dynamic Threshold Detection for STT-MRAM

Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising candidate for the next generation non-volatile memory technologies. However, due to the process variation and the thermal fluctuation, the reliability will be severely affected by the unknown offset of the channel. In this paper, we propose an FPGA architecture of neural network-based dynamic threshold detector for STT-MRAM to tackle the unknown offset. The hardware architecture of neural network (NN) is implemented on Intel FPGA Cyclone V 5CGXFC9D6F27C7 and achieve the similar performance as the software implementation. Then, in order to reduce the resource consumption, we try to decrease the data precision during processing and storage. Finally, we accomplish FPGA-based dynamic threshold detector (DTD) [1] to reduce the time and power cost of NN.