Hardware Emulation of a Biorthogonal Wavelet Transform-Based Heart Rate Monitoring Device

In this work, a low-power, area-efficient, and high-performance electrocardiogram (ECG) detector that can be used in modern implantable cardiac pacemaker systems is proposed. Qualitative and quantitative analysis indicates that the Biorthogonal-3.1 wavelet transform combined with adaptive slope prediction is best suited to detect various ECG peaks by effectively denoising various artifacts present in an ECG signal. A demand-based wavelet filter bank (WFB) architecture consisting of a series combination of three lowpass filters is the primary reason for the low-power requirements of the circuit. Power consumption and area requirements of the circuit are further reduced by realizing the lowpass filters using lattice wave digital filter realization that reduces the requirement of delay elements, and multipliers count by 80% and 75%, respectively. The proposed ECG denoising scheme using the biorthogonal 3.1 wavelet transform generates a smoother denoised ECG wave by retaining the important morphology of an ECG signal. Adaptive slope prediction criterion-based ECG processing and detection schemes achieve a high detection accuracy of 99.90%, with the lowest error of 0.002%. The proposed scheme is capable of distinguishing between a normal ECG, paced ECG, arrhythmic ECG, and low and high-resolution ECG. The proposed algorithm is then emulated on the Xilinx®-Virtex®-7 FPGA hardware platform. Power consumption, area, delay, and switching energy of the proposed ECG processing scheme are reduced when compared to existing ECG detection schemes and are found to be of 0.493 μW, 1.1 mm2, 10 ns, and 4.93 μJ, respectively.