Latchup Test Structure Optimization in Advanced CMOS Technologies

Latchup sensitivity is often measured with a single, collinear PNPN test victim. This method is insufficient for measuring the latchup performance of advanced CMOS technology because it does not represent real-world designs. As a result, the predicted latchup performance is too optimistic. In this work, more realistic latchup test structures are discussed. By adopting these new structures, a more accurate prediction of product-level latchup sensitivity can be measured with test structures, enabling more optimized designs with fewer design revisions.