Empirical ESD Modeling of Multi-Gate ESD Transistors

ESD transistors with multiple parallel gate terminals were measured by TLP using worst-case scenario set-up. The resulting Empirical ESD Models for multiple gates ESD transistors employ behavioral code and contain the dependency of Vt1 and post-snapback characteristics on the sizes of the multiple gates of the ESD transistor. Simulation of HBM stress, employing E2M of multi-gate ESD transistors, was demonstrated. Finally, the dependency of the coupling between the parallel gates, on the layout of the ESD transistor, was investigated.