An Energy Efficient 16T Hybrid-CMOS Full Adder using Novel Full Swing XNOR Logic

In this paper, an energy efficient novel hybrid-CMOS 1-bit Full Adder based on XNOR-XNOR logic is presented. The proposed full adder is designed with 16 transistors, whereas the novel full swing XNOR logic is implemented using 5 transistors. The proposed hybrid full adder is designed in Cadence Virtuoso and the simulation work is carried out in Spectre simulator at
$45nm$
technology node and 0.8V of power supply. The proposed work has been compared with recent reported work based on several hybrid design style. The propagation delay, power dissipation and energy consumption are 207.2pS, 45.32nW and 9.39aJ respectively for the proposed hybrid full adder. Addition to these, the effect of process and temperature variation has been analyzed. The novel full swing XNOR helps to improve the nose margin of the proposed HFA. A 4-bit binary adder is also implemented using the proposed 1-bit hybrid full adder for the purpose of test and verification. The propagation delay and power dissipation are 551pS and 168.83nW respectively for the 4-bit binary adder.