High-Throughput Synthesizable Synchronization FIFOs for Mixed-Timing NoCs

This paper presents a family of modular, standard-cell-based interfaces for crossing between asynchronous and synchronous timing domains. These FIFOs have interchangeable input and output interfaces for edge-triggered synchronous communication and for the asP* asynchronous pulse-based handshake protocol. The FIFO capacity, synchronizer latency and interface protocols are independent parameters, allowing the FIFO to be easily configured for different requirements. The modular design makes the FIFO ideal for use in system-on-chip applications, where multiple functional blocks operating at different clock frequencies communicate using an asynchronous network-on-chip. They provide high-throughput communication and hide most of the synchronization latency. Our designs are fully synthesizable using widely available standard cell libraries and a standard ASIC design flow. We generate layoutS for several different synchronous and asynchronous FIFOs. All instances can operate at speeds greater than 1.45 GHz under worst-case conditions when implemented in a 65nm CMOS process.