Resistive opens in a class of CMOS latches: analysis and DFT

The behavior of a class of CMOS latches in the presence of resistive opens is investigated. The detectability of resistive opens by delay testing is analyzed. The resistive opens in the driver and inverter stages are classified according to its behavior. Opens occur in conducting paths, single open gates and multiple open gates. Opens in conducting paths are the easiest to detect and opens in single open gates are the most difficult to detect. Resistive opens in the clocked inverter deserves special attention. Some open locations in this stage are well known as undetectable by a traditional voltage test. A DFT (Design for Testability) approach is proposed for opens in conducting paths of the clocked inverter stage. The cost of the DFT approach in terms of speed degradation and area overhead is evaluated. A comparison is made with other testable latches structures proposed in the literature. Other two interesting cases of opens in the clocked inverter have been found.