High-level design of HEVC intra prediction algorithm

In recent years, most of developers work continuously in order to improve design performances in term of energy efficiency and performances. Therefore, the adoption of high-level synthesis (HLS) techniques can help to reach these requirements, especially when dealing with such complex applications like High Efficiency Video Coding standard (HEVC). This paper discusses a case study of intra prediction algorithm of HEVC using HLS designing method. For this experiment, we used the version 10 of HEVC Test Model (HM) reference software which involves more than 300 functions and over 9000 lines of code. Moreover, this algorithm is implemented in SW/HW environment using Xilinx ZC 702 based-platform. Finally, the experimental results prove that the hardware implementation is able to process 51 video frames per seconde of Full HD (1920xl080p) resolution. However, the SW/HW design can only decode 15 frames per second for 240p video resolutions with a gain of 6% in frame rate and 70% in power consumption relative to SW implementation.