Comparative Analysis of FPGA Based Hardware Design of Dynamic Time Warping Algorithm using Different Multiplier Architectures

Dynamic Time Warping algorithm is used widely in speech recognition applications to provide a measure of similarity between two time-varying sequences. It finds its use in the speech processing applications due to the fact that the two sequences to be compared may be of different lengths and Euclidean distance computation may not give a true picture of the diversity between the two sequences. This algorithm involves a lot of computational complexity because of the large number of multiplication operations involved in its implementation. Also, the time delay is quite significant. In this work, hardware implementation of DTW matrix computation along with a comparative analysis using different multipliers for studying the hardware utilization statistics and time delay involved in the operation has been done. Verilog Hardware Description language (HDL) has been used and all the simulations have been performed on Model Sim.