Design of High Speed and Low Offset SR Latch Based Dynamic Comparator

Dynamic comparators find application in data converters, sense amplifiers, RFID and data-receivers. Here a new design is proposed that appends an SR latch, achieving a very high speed at low offset voltage with low kickback noise. The comparator has 3-stages, 2 of which are at the differential sensing stage while the 3^rd is formed by the SR latch at the output stage. The proposed design is done on UMC 180 nm standard CMOS platform. The clock frequency is set at 100 MHz and the supply at 1.8V. Simulation is carried out using CADENCE Virtuoso EDA tool. The design is validated and benchmarked against other reported candidates where it proves to be the design of choice when operated at low power as an environ-friendly option, supporting humanitarian cause.