A high-performance low-power static differential double edge-triggered flip-flop

A new static differential double edge-triggered flip-flop is proposed. In order to ensure the double edge triggering operation, a narrow pulse is generated after each clocking edge, by means of clock racing. Compared to existing double edge-triggered flip-flops, the presented circuit configuration presents improved delay characteristics, reduced power consumption, while keeps the total transistor count low. Further power and transistor savings can be achieved by applying the narrow pulse to more than one similar adjacent DET flip-flops.