Development of a low-power SRAM compiler

With the proliferation of portable consumer electronics, power-consumption becomes a key design criterion, while the speed of memories is still the bottleneck for high-speed applications. In this paper, we discuss the development of an SRAM compiler with the capability to choose between a low-power and a high-speed SRAM. Experimental results show that the low-power version of our 1-kB SRAM can function at a minimum operating voltage of 2.1 V and dissipates 17.4 mW of average power at 20 MHz.