Security Issues in the Design of Chips for IoT

The Internet of Things presents new challenges in the design of computing and electronics systems. The main challenges are related to the optimization of the devices connected to the internet, mainly power consumption, but also reliability and security. In this paper, the focus is on security issues, primarily the ones related to intellectual property at the layout level. The physical design of devices for IoT can use several approaches to increase the difficulty of reverse engineering. One is the use of camouflage, which means the insertion of dummy segments of metal or dummy contacts/vias, just to become more difficult the reverse engineering. Another is the use of transistor reordering, which allows implementing a function using different topologies or transistor orderings. The use of layout design automation also helps to obtain different layouts for the same logic function, even a way to make reverse engineering difficult. These layout design techniques are explored in this paper, showing how we can improve security at the physical design level of abstraction.