Asynchronous Bundled-Data Pipeline Cryptographic Architecture with RDI Countermeasure

This work proposed an Asynchronous Bundled-Data Pipelined Architecture for the Data Encryption Standard (DES) Algorithm using Random Delay Insertion (RDI) Countermeasure. The objective was to achieve robustness against Differential Power Analysis (DPA). This architecture was implemented in 4 different ways varying according some architectural-level decisions. All versions of this architecture presented robustness against DPA by means of time-misalignment in the power traces. This protection was achieved at the cost of an average area increasement of 8.455 times and an average throughput increasement of 17 times when compared to a regular synchronous implementation. Comparing with an asynchronous implementation in literature, the architecture achieved a reduction of 37.367% in area overhead and an increseament of 10.8 times in the throughput ratio.