Multirate-cascade sigma-delta (MC-SD) modulators

New high-speed sigma-delta (SD) analog to digital converters (ADC's) are required for xDSL and RF receivers. As sampling frequency is upper limited by the amplifier bandwidth and power consumption, these high-speed, low-power converters operate with a small oversampling ratio. Usually, they are high-order cascade structures with a multibit quantizer in the last stage. All previously reported approaches use a unique sampling frequency. This paper shows that multirating is a useful technique to reduce power consumption in high speed SD converters. To this end, a multirate-cascade SD modulator is proposed where a low oversampling frequency is used in the first stage(s) of a cascade converter.