A 2.5 Gbit/s CMOS PLL for data/clock recovery without frequency divider

A phase locked loop (PLL) design based on a new phase detector (PD) is presented. It can be used as a part of data/clock recovery (DCR) systems targeting the applications of 2 Gbit/s-3 Gbit/s range Ethernet and optic fiber transceivers in current semiconductor processes. A key component in the circuit is a new non-sequential PD that provides for very high speed operation. Using TSMC 0.25 u CMOS process device models and the HSPICE simulator, results show that the PLL can operate at 2.5 GHz over process corners and a 0/spl deg/C to 100/spl deg/C temperature range. Total power dissipation is 40 mW with a single 2.5 V power supply.