Improving Test Coverage of Hi-Reliability ASIC Designs with Test Point Insertion for Space Applications

The rapid growth in semiconductor technology has paved way for complex designs with high device densities. This has given rise to more challenges in device testing. Towards miniaturization of electronics systems in spacecraft's, usage of ASICs and FPGAs with fault tolerant (FT) design techniques are increasing. Incorporating fault tolerance with Triple Modular Redundancy (TMR) logics introduces the controllability and observability issues in the design and hence reduces the test coverage. Reduction of test coverage leads to usage of inferior or faulty devices (test escapes) and hence impacts the system reliability. This demands high quality of tests with less patterns and reduced test time. This can be achieved with a nominal increase in area and performance, by using test points. This article proposes a novel method of automatic test point insertion using EDA tools for improving test coverage of a design consisting of TMR logics. The proposed method has achieved the improvement of test coverage from 81.7% to 97.1% for Command Distribution (CD) ASIC (about 1.5 million gates) with bare minimum area overhead and without degrading the performance of the device.