Highly Scalable Processor Architecture for Reinforcement Learning

Q-Learning is also referred as a reinforcement learning method. Its main advantage is that of obtaining a near optimal policy while interfacing with an unknown model. This paper presents a hardware architecture for Q-Learning, which is efficient in terms of running a larger set of Q-Learning problem sizes. The proposed research work presents the method and resource utilization, when implemented in FPGA, and algorithm involved in the proposed hardware. The proposed algorithm consumes a negligible area when compared to the parallel implementation of Q learning algorithm.