Design and synthesis of reversible data selectors for low power application

Reversible logic design has paved way for a new area of research and is gaining a lot of research attention as it is very useful in various areas such as low power VLSI design, quantum computing, and nanotechnology. Combinational logic dissipates the significant amount of energy due to bit loss. So, if circuits are designed using reversible logic, where information bits are not destroyed and reduced the significant amount of power dissipation. Reversible circuits are designed using parity preserving gates, which has the property of detecting not more than a single error in the circuit's primary output. If a circuit is both reversible and fault tolerant, it can recover bit-loss at the input as well as bit-error at output. This paper presents the design and FPGA synthesis of optimized data selectors. This paper also highlights the low switching power consumption characteristics of data selectors, which were typically around 1 to 3μW that finds its use in low power applications that are targeting ultra-speed.