Model-Based Design of A Real-time Context-Aware Speech Enhancement System on an FPGA-SoC

Modern Implementation platforms are suitable for realizing complex adaptive systems that require the system to adjust its behavior to satisfy variable design goals. A prominent example is context-aware systems that are capable of automatically adapting their operations according to the dynamic system context. This work introduces a model-based design flow for a context-aware FPGA-SoC-based system in the speech enhancement domain. The proposed design flow implements the adaptive context-awareness by exploiting the runtime reconfiguration feature of the state-of-the-art FPGA-SoC devices. By employing the proposed design flow and architecture, a context-aware speech enhancement application can be implemented in such a way that it is able to change its own processing algorithm to meet runtime goals and can lead to the area reduction of the FPGA by using one hardware-accelerated algorithm at a time.