Comparative Study and Design of Current Starved Ring Oscillators in 16 nm Technology

In this brief, different characteristics of current starved ring oscillator (CSRO) circuits are investigated and four new designs are proposed. A new parameter, known as phase noise bandwidth product (PNBP), is also proposed to address the trade-off between phase noise performance and frequency tuning range while designing ring oscillators (ROs). The proposed circuits are compared with existing architectures in terms of power consumption, frequency bandwidth, maximum frequency, phase noise, power delay product (PDP) and PNBP. For performance evaluation, three-stage CSROs have been implemented in Cadence software using the 16 nm PTM High Performance (HP) technology model. Simulation results demonstrate that two newly proposed CSRO architectures using one NMOS sink or one PMOS source have similar optimum results in terms of PDP and PNBP as the existing CSRO using an output switch scheme, but with an advantage of lower area requirement. Moreover, all four proposed architectures show improved performance in terms of PDP and PNBP compared to conventional CSRO. The performance of the CSROs is also observed and compared with respect to the variations in process-voltage-temperature (PVT) parameters.