Design and Rapid Assessment of Efficient On-Chip ESD Protection Strategy

This study details a newly proposed technique for the fast and efficient design of on-chip electrostatic discharge (ESD) protection strategy using developed coupling transfer impedance function. The transfer coupling characteristics from the zapping point to the victim location can be computed using the proposed coupling transfer gain function. The transfer characteristics in terms of coupling gain function can be integrated with ESD current source in the SPICE type circuit simulator for the fast and efficient analysis of induced ESD coupling noise and the design of the appropriate ESD protection scheme with the suitable choice of ESD protection device (diodes etc.). The study explains the different protection schemes i.e. primary, secondary and double ESD protection schemes and the effect of the selected diode types on the employed protection strategy.