A Dynamic General Accelerator for Integer and Fixed-Point Processing

Coarse-grained reconfigurable arrays (CGRAs) are used as low-power and high-performance accelerators in the processors of the Internet of Things (IoT) and embedded systems to accelerate the computation of intensive tasks. These accelerators speedup loops, including integer and fixed-point instructions of computation-intensive applications, in multimedia, voice coding, and encryption algorithms. The design of an efficient compiler that could map the compiled assembly codes to CGRA is a serious challenge. Even with existing such compiler, the compiled programs are dependent on the hardware of CGRA and processor, i.e., the accelerator is not transparent to compilers and applications. This article proposes a novel accelerator that its CGRA is concatenated with the main ALU of the processor to speedup the execution of integer and logical applications. The proposed accelerator and its hardware-based implemented mapping technique are completely transparent to the compiler, OS, user, and applications. This architecture overcomes the dependence challenge mentioned earlier. The simulation results indicate that the proposed architecture improves the performance and energy consumption on average by 15.8% and 8% in comparison with the baseline architecture, respectively, whereas the area and power overhead of the proposed architecture when the CGRA is used at its optimum case are 4.47% and 4.43%, respectively.