Development of 500mm×500mm Fan-out panel level packaging for heterogeneous chip integration

Fan-out packaging has received growing attention recently due to its high integration capacity, higher pin counts, better performance, and easier for system in package. The fan-out packaging covers an increasing range of applications, from RF system, MEMS sensors antenna-in-package, to system in package. Compared to the fan-out wafer level packaging (FOWLP), the fan-out panel level packaging (FOPLP) has potential cost benefit and higher manufacturing efficiency. At the same time, FOPLP has higher carrier usage ratio of 95% higher than the ratio of 85% of FOWLP. In this paper, the design, process and fabrication of a heterogeneous integration of four chips by FOPLP with chip-first and die face-down formation are investigated. The panel size is 500mm×500m, and contains 1080 units of test vehicle 12mm×12mm. There are four different size chips with daisy chain are integrated into the test vehicle. The test vehicle have 3 layers of PI and 2 layers of RDL, and have more than 500 BGA balls with pitch 400um. The minimum width and space of RDL1 layers can reach 10um/10um. Several key modules for panel level packaging like die pick and place, compression molding, tempoary bonding and debonding, panel lithography, RDL fabrication have been introduced.