FPGA Implementation of LDPC Encoder Architecture for Wireless Communication Standards

In this paper a pipeline architecture is proposed for FPGA implementation of a quasi-cyclic LDPC (QC-LDPC) encoder. The results are provided for implementation on a Xilinx ZYNQ-7 ZC706 Evaluation Board for code with rate 5/6 and block lengths from 576 to 2304. The design is parameterized and can be easily rebuilt to support various code rates and code lengths. The base matrices H and code parameters are taken from the IEEE 802.16e standard. The number of logic elements (LUT), clock speed, and throughput of the encoder are presented for different code lengths. The throughput of up to 16 Gbps for IEEE 802.16e codes has been achieved.