Non-Dynamic Power Reduction Techniques for Digital VLSI Circuits: Classification and Review

This paper reviews different methods to reduce the power leakage in dynamic digital circuits while sustaining the previous logic state. The transistor length has continuously been reduced in designing the VLSI circuits. This reduction of length shrinks the threshold voltage, which surges the subthreshold leakage current, as a side effect. This has directed towards an overwhelming increase in the concerns about leakage power dissipation. Numerous systems have been projected to decrease the subthreshold leakage current. Each technique, reviewed in this paper, reduces the leakage power but have some disadvantage associated, limiting their use. Modification in the circuits has been studied too, which has certain advantages over previous methods with lesser disadvantages.