Design and Verification of Memory Elements using Python

Digital VLSI Design involves writing synthesizable RTL code using hardware description languages like VHDL/Verilog or hardware verification language like SystemVerilog. After the synthesis of the code, digital models are produced. In any hardware design, the verification of the design will hold the topmost priority and is also a process that takes up a lot of effort and time. In high-level synthesis (HLS), the design is specified in a high-level language (HLL) like C, and then converted to hardware description language (HDL) using HLS tools, that can be synthesized into a Xilinx field programmable gate array (FPGA). Simulation is a process that helps the user to verify and validate the functionality of the design, making sure it matches the design specifications. Co-simulation is used to perform cross-language verification of the design. The HLS tools only convert the source code into HDL. The testbench written in the high-level language can be re-used for verification using co-simulation. However, co-simulation may not always work due to some restrictions in the tool. Without co-simulation, along with the testbench written in the high-level language another testbench will have to be written in HDL manually by the user in order to perform the primary verification of the converted code. Therefore, in order to reduce the time taken to write the HDL testbenches in such scenarios, the paper aims to generate testbenches in SystemVerilog using a Python source script. In this paper, memory elements like queue and FIFO will be designed in C and verified using the generated SystemVerilog testbench.