Efficient Adjacent 3D Parity Error Detection and Correction Codes for Embedded Memories

The detection and correction of errors during memory read operation performed per clock cycle play a significant role in at-speed testing of embedded memories. The majority of key role applications like in satellites, medical database, etc require a faster and perfect recovery of data stored. This paper aims at processing the multiple adjacent errors per clock cycle. The codes use XORing of data bits to obtain parity bits and extract the syndrome for error evaluation and correction. The devised code is capable of correcting 32 adjacent data bits among 64 data bits than the existing codes. The encoder and decoder codes are modeled in Verilog HDL and verified in Xilinx Vivado Tool for the Zynq 7000 series FPGA XC7Z020-1CLG484. Interestingly the code rate can be increased with lower bit overhead.