Energy Efficient Multiplier for Reconfigurable Digital filter

The growth of personal computing devices as portable desktops, personal digital assistants, multimedia and personal computers demands a complex functionality with efficient computations. Digital systems with present day technologies possess a very high computing capability that makes powerful workstations. The demand for low power consumption is prominently increasing as the device feature size shrinks into submicron dimensions. Power dissipation can become the bottleneck for the current designs because of battery life and cooling requirements of portable equipment's. Excessive power consumption degrades the reliability and limits the transistor integration on a chip. With, ever increasing quest for higher computing power on battery operated devices, design emphasis on optimizing area, power with high performance. The total power dissipation of the proposed compressor is found to be 11.796 μW and 5.168 μW with the corresponding delay of 0.649 ns and 0.437 ns for 180 nm and 90 nm technologies respectively. It reveals a PDP reduction of the proposed compressor to be 5.50% to 15.83% for 180 nm technology, 4.48% to 14.89% for 90 nm technology compared with other state-of-the-art designs. This suggests the suitability of the proposed compressor design for portable applications. An 8-bit Wallace tree multiplier is designed using the proposed compressor and other state-of-the-art designs. From the comparison, it is seen that the multiplier design using proposed compressor architecture achieves better performance in terms of PDP compared to other state-of-the- art designs.