A Compile-Time Framework for Tolerating Read Disturbance in STT-RAM

Spin-transfer torque magnetic random access memory (STT-RAM) is one of the most promising candidates for next-generation on-chip memories. While STT-RAM offers high density, negligible leakage power, and fast access speed, it also suffers from read-disturbance errors, that is, read operations might accidentally change the value of the accessed memory location. Although these errors could be mitigated by applying restore-after-read operations, the energy overhead would be significant. To reduce such overhead, this article presents an application-level and architecture-independent framework, which selectively inserts restore operations under the guidance of a compiler. This work first introduces a new concept of disturbance chain and then analyzes the vulnerability of each load instruction on a chain to read disturbance errors. This work further proposes a number of compile-time code optimizations to reduce the number of vulnerable loads and hence the associated restore overhead. The proposed compiler optimizations are implemented in LLVM. Experiments in Gem5 show up to 98.6% reduction in the number of restore operations and 48% savings of the energy overhead while maintaining 99.8% coverage of read disturbance errors.