Top-down RSFQ logic design based on a binary decision diagram

We have proposed a top-down design methodology for RSFQ logic circuits using a binary decision diagram (BDD). The BDD is a way to represent a logical function by a directed graph, which consists of binary switches having one input and two outputs. The important features of the BDD RSFQ logic circuits are a small number of primitives, dual rail and non-clocked logic style, and a small gate count. We have constructed a cell library for the BDD RSFQ logic design, which is composed of five square basic cells. Any logic function can be constructed by simply connecting the library cells. CAD tools for the logic level simulation, the circuit simulation and a layout view extraction have been developed to carry out the top-down RSFQ logic design on the Cadence CAD environment. A design flow of the RSFQ full adder is demonstrated to show the potential of the top-down design methodology for the design of large-scale RSFQ integrated circuits.