Backplane Channel Design Exploration at 112 Gbps Using Channel Operating Margin (COM)

High speed digital design is constantly attracting the attention of the electronic industry due to the constant development of telecommunication standards, with the consequence of ever growing data rate and new modulation schemes. The Channel Operating Margin (COM) comes up as a powerful tool for channel and physical layer designers to explore the design space at an early stage, as well as to optimize the channel physical parameters, thus overcoming the classic channel performance metrics such as eye diagram and BER. The analysis of the test cases proposed herein will guide through the use of COM and the channel analysis by investigating a 112 Gbps PAM4 chip-to-chip communication over a complex channel composed of a host board, a mezzanine connector, and a daughter card. Accurate analysis of these elements is carried out based on the connector characterization by measurements and full wave models; the PCBs, instead, are modeled as multiconductor transmission lines to resemble the typical configuration of coupled differential striplines. A comprehensive discussion of the COM results set relevant guidelines for a pre-layout analysis of such high speed communication channels.