A Highly Stable and Robust 7T SRAM Cell using Memristor

The ever-growing needs for processing on system-on-chip (SoC) demands us to scale down the Static RAM (SRAM) cell which occupies around 65-75% area of SoCs. Continued scaling procedure have decreased the read and write stability of SRAMs cell with increased delay. Emerging technologies like Memristor is used for smaller area consumption than a standard CMOS design without compromising the device's functionality. A seven transistor(7T) cell at 7nm feature size is proposed to accomplish improvements in noise margins. In the proposed architecture 7nm model card used is taken from Predictive Technology Model (PTM) and all the simulations are done in Cadence Virtuoso tool. The Static Noise Margin (SNM), Read Noise Margin (RNM), Write Noise Margin (WNM) of the proposed architecture are 210mv, 210mv, 145mv respectively. The read time of 1-bit cell is 5ps and write time is 17.6ps with an estimated area of 0.0291μm
²
.