KARNA for a Trustable Hardware

Due to globalization, hardware threats are emerging challenges for the design engineers in the integrated chip (IC)manufacturing unit. Nowadays application-specific integrated circuits (ASICs) are mostly replaced with reconfigurable field-programmable gate array (FPGAs), to provide a flexible system to support many applications. The secured reconfigurable hardware is the need for end-users to use the hardware in several trustable applications. The proposed method delivers secured hardware, such that whenever a malicious activity occurs, KARNA an embedded logic will detect the threat with the proof modeled in the design. To minimize computational complexity, specific nodes are selected to model the proof. So that KARNA will check only those nodes and this increases the detection accuracy as well. The proposed framework is validated on ISCAS'85 benchmark circuits, implemented on Xilinx Spartan 6 field-programmable gate array (FPGA), and evaluated to provide a trustable platform with PCH with minimal design overhead and accurate detection coverage.