Simulator-Based Framework towards Improved Cache Predictability for Multi-Core Avionic Systems

Avionics are highly regulated systems and their criticality requires determinism. Single-core systems have a single processor running, hence only one execution flow, making them easily predictable in execution. However, manufacturers are moving towards multi-core processors manufacturing only. Avionics systems are thus compelled to transition from single-core to multi-core architectures. Mechanisms to mitigate the loss of determinism when using multi-core architectures must be developed to take profit from the parallelism offered by them. This work focuses on partitioned avionics systems and more precisely Real-Time Operating Systems (RTOS) in avionics. We propose a trace-based framework that analyzes application be-havior. It also gives cache information through an integrated cache simulator. To validate our framework, we integrated a cache locking selection algorithm. When running tests through our framework and its embedded simulator, we have an improvement in execution predictability and a reduction of interference (over 25%) after locking data in the cache.