Double Feature Extraction Method for Wafer Map Classification Based on Convolution Neural Network

The individual components of an integrated circuit (IC) are extremely small and its production demands precision at an atomic level. ICs are made by creating circuit structures on a wafer made out of very pure semiconducting material, typically silicon, and interconnecting the structures using wires. In order to produce high density IC, the wafer surface must be extremely clean and the circuit layers fabricated on the previous wafer should be aligned. If these conditions are not satisfied, the high density structure may collapse. To prevent this from happening, the wafers must be constantly cleaned to avoid contamination, and to remove the left-over of the previous process steps. Then, automatic defect classification (ADC) is used to identify and classify wafer surface defects using scanning electron microscope images. However, the classification performance of current ADC systems is poor. If the defects could be classified correctly, then the root of the fabrication problem can be recognized and eventually resolved. Machine learning techniques have been widely accepted and are well suited for such classification problems. In this paper, we propose double feature extraction method based on convolution neural network. The proposed model uses the Radon transform for the first feature extraction, and then input this feature into the convolution layer for the second feature extraction. Experiments with real-world data set verified that the proposed method achieves high defect classification performance, defect pattern recognition accuracy up to 98.5%, and we confirmed the effectiveness of the proposed feature extraction technique.