Temperature investigation of a Novel 3nm TF-Bulk FinFET for Improved Performance

In this investigation, a novel Truncated Fin (TF) Junctionless (JL) bulk FinFET is compared over it's conventional structure. This paper is the analysis of highperformance temperature characteristics of a (JL) FinFET at the scale of gate length 3 nm investigated on Silvaco TCAD EDA Tools. This (TF) FinFET is the truncation of the fin at it's lower end (near it's interface with substrate) to have good impact. Moreover, the material and width of substrate are decided such that there will be minimum leakage of drain current through it. The procurement of this work is reduction of SCEs marked as S.S=66.5mV/dec and \pmbDIBL=2.5\pmbmV/\pmbV at room temperature in case of TF-FinFET. The enhancement in device performance can be inspected by some more SCEs parameters, which actually vary when channel length get comparable to the depletion width of Source and drain junctions, such as drain current at OFF state (which found out to be decreased by 81.5 times in TF-FinFET at 300K), substrate current (which stood lowest at 500K and highest at 200K), switching ratio denoted by “ ION/IOFF” (grown by 120 times in case of TF-FinFET at 200K) and the threshold voltage “ vth” of the simulated devices (which was found to be 0.256 V for TF-FinFET and 0.148 V for conventional FinFET at 200K). These parameters are best observed between 200K to 300K.