System on Chip Implementation of Low Complex Orthogonal Matching Pursuit Algorithm on FPGA

This paper presents a System on Chip (SoC) implementation of the standard Orthogonal Matching Pursuit (OMP) algorithm using matrix partition and Modified Cholesky factorization techniques. A fixed-point optimized hardware Intellectual Property (IP) of the OMP algorithm is designed using a high-level synthesis (HLS) tool. The execution time of the optimized fixed-point hardware IP for different sparsity is compared with the equivalent fixed-point and floating-point realization on the Zynq-7000 Field Programmable Gate Array (FPGA). Intel senor data is used for verifying the functionality of the SoC design. The experiment is carried out for signal length (N), compressed signal length (M) as 256 and 84 respectively with different sparsity factor (K) as 5, 10 and 15. The acceleration factor of 70 and 73 is achieved for the fixed-point and floating-point software realization of the OMP algorithm, respectively.