Design of 4-bit ALU using TEAM Memristor Model and CMOS Logic

This paper presents a modular design of Arithmetic Logic Unit based on memristor and CMOS logic. The proposal has been implemented using ThrEshold Adaptive Memristor model (TEAM). The functional verification is done using simulations on Cadence Virtuoso tool. There is significant reduction in transistor count using the proposed approach which will lead to significant decrease in overall implementation area. Comparison of this approach helps us to reduce the chip area as well as power utilization and it is reliable as well.