Static Noise Margin Analysis of Various SRAM Array

Decreasing the power consumption and growing the noise margin have turn out to be two imperative topics in the artwork SRAM design. Recent works have proven that the traditional 6T SRAM suffer stability degradation, as a consequence, 8T and 10T designs had been implemented to enhancing the cellular stability. The objective of this work is to describe the design and cadence implementation of a 256-byte SRAM using 90nm CMOS technology with 3 different architectures-(1)6T SRAM (2)8T SRAM (3) 10T SRAM and their comparison is done on the factor of static noise margin. By using this analysis, we can clarify the stability of memory cells.