Low-Power and Area-Efficient Finite Field Multiplier Architecture Based on Irreducible All-One Polynomials

This paper presents a low-power and area-efficient finite field multiplier based on irreducible all-one polynomials (AOP). The proposed architecture implements the AOP multiplication algorithm in three stages, which are reduction network, AND network (multiplication), and three input XOR tree (accumulation), while state-of-the-art implementations distribute reduction, multiplication and accumulation operations in a systolic array. The optimization reduces the overall number of sequential instances and provides lower pipeline latency compared to literature. This leads to the reduction of power dissipation and area for a targeted system clock frequency. Both the previously reported and the proposed architectures have been implemented in Verilog for three different and relevant binary field sizes using TSMC 130-nm standard cell library from Artisan Components, and have been synthesized with a 100 MHz system clock frequency target using the Cadence Genus Synthesis tool. The proposed architecture offers 23%, 41%, and 20% reduction in average leakage, dynamic power, and area, respectively, compared to state of the art. The pipelined latency advantage can be translated to further power dissipation reduction by targeting a lower clock frequency in applications where single AOP multiplication execution time is more important than pipeline throughput. Thus, the proposed architecture is better suited for energy-efficient portable systems, including wireless sensors.