Ratioed Logic Comparator Based Digital LDO Regulator in 22nm FDSOI

This paper presents a fast and an efficient digital LDO (DLDO) regulator utilizing a clock-less ratioed logic comparator (RLC). In addition to eliminating the clock, the proposed RLC-DLDO removes the shift registers used in the conventional DLDO. It achieves a transient speed improvement in the ns range and a quiescent current reduction by 9X over the conventional DLDO design that targets μA load current. The RLC-DLDO consists of RLC, PMOS power switches and control unit. The RLC compares between the reference and the load voltage and generates a single bit that turns on/off the PMOS switches. Unlike the clocked comparator, the RLC is an event-driven design that continuously responds to the voltage difference. The control unit provides digital bits to control the power switches and the RLC circuit in order to support different output voltage levels. The RLC-DLDO has an input voltage range between 0.8V and 0.6V and generates an output voltage range between 0.7V to 0.5V for load current between 10μA and 500μA. The design is implemented in 22nm FDSOI and occupies an active area of 0.0171mm
²
. The simulation results show that the peak efficiency is 99.9% and the load transient response time is 5ns at V
L
=0.5V.